Phase mixer and delay locked loop including the same

ABSTRACT

A phase mixer includes a first driver configured to drive a first input signal to a mixing node with a driving force determined by a first setting value, a second driver configured to drive a second input signal to the mixing node with a driving force determined by a second setting value, and a slew rate control unit configured to control a slew rate at the mixing node.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2011-0107599, filed on Oct. 20, 2011, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a phase mixerand a delay locked loop.

2. Description of the Related Art

A phase mixer is a circuit which mixes two signals with different phasesand generates a mixed signal with an intermediate phase between thephases of the two signals. The phase of the mixed signal generated bythe phase mixer is changed depending upon at which ratio the two signalsare mixed. For example, if a first signal and a second signal are mixedat the ratio of M:N, as M/N increases, the phase of a mixed signalapproaches the phase of the first signal, and as M/N decreases, thephase of a mixed signal approaches the phase of the second signal. Sincethe phase mixer can finely control the phase of a mixed signal betweenthe phases of two signals, the phase mixer is used in a delay lockedloop (DLL), etc.

FIG. 1 is a configuration diagram of a conventional phase mixer.

Referring to FIG. 1, the phase mixer includes a first driver 110, asecond driver 120, and an buffer 130.

Hereinafter, operations of the phase mixer will be described withreference to FIG. 1.

The first driver 110 drives a first clock FCLK to a mixing node MN witha driving force that is determined in response to a code CD<0:3>. Forthis operation, the first driver 110 includes a plurality of inverters111 to 114 which are activated or deactivated by the respective bitsCD<0> to CD<3> of the code CD<0:3>.

The second driver 120 drives a second clock SCLK to the mixing node MNwith a driving force that is determined in response to an inverted codeCDB<0:3>, which is obtained by inverting the code CD<0:3>. According toan example, the second driver 120 includes a plurality of inverters 121to 124, which are activated or deactivated by the respective bits CDB<0>to CDB<3> of the inverted code CDB<0:3>. For illustration purposes, therespective bits CD<0> to CD<3> of the code CD<0:3> and the respectivebits CDB<0> to CDB<3> of the inverted code CDB<0:3> are in invertedrelationships.

The buffer 130 buffers the signal of the mixing node MN and outputs thebuffered signal to an output node OUT. For this operation, the buffer130 may be an inverter which outputs a high level to the output node OUTwhen the voltage level of the mixing node MN is lower than a referencelevel (a logic threshold, that is, a reference voltage fordiscriminating a high level and a low level) and outputs a low level tothe output node OUT when the voltage level of the mixing node MN ishigher than the reference level.

The first driver 110 drives the first clock FCLK output to the mixingnode MN more strongly as the number of bits with a high value of ‘1’increases among the respective bits of the code CD<0:3>, and the seconddriver 120 drives the second clock SCLK output to the mixing node MNmore strongly as the number of bits with a high value of ‘1’ increasesamong the respective bits of the inverted code CDB<0:3>. For example, ifthe value of the code CD<0:3> is ‘0001’ (the value of the inverted codeCDB<0:3> is ‘1110’), a ratio between the driving force for driving thefirst clock FCLK to the mixing node MN and the driving force for drivingthe second clock SCLK to the mixing node MN becomes 1:3. If the value ofthe code CD<0:3> is ‘0111’ (the value of the inverted code CDB<0:3> is‘1000’), a ratio between the driving force for driving the first clockFCLK to the mixing node MN and the driving force for driving the secondclock SCLK to the mixing node MN becomes 3:1. If the value of the codeCD<0:3> is ‘1111’ (the value of the inverted code CDB<0:3> is ‘0000’),for example, only the first clock FCLK is driven to the mixing node MN,and if the value of the code CD<0:3> is ‘0000’ (the value of theinverted code CDB<0:3> is ‘1111’), for example, only the second clockSCLK is driven to the mixing node MN. The phase of the signal(hereinafter, referred to as an output signal OUT) outputted to theoutput node OUT is changed according to the driving forces for drivingthe first clock FCLK and the second clock SCLK to the mixing node MN.

The phase mixer may be used as a fine delay line for finely controllingthe phase of a clock in a delay locked loop (DLL). As to details ofusing a phase mixer as a fine delay line of a delay locked loop, suchdetails are disclosed in Korean Patent Application No. 10-2009-0133426(entitled “a delay locked loop circuit”), which is incorporated hereinby reference in its entirety.

When a phase mixer is used in a delay locked loop, in order to suppressthe occurrence of a jitter, a phase change amount in the output signalof the phase mixer is constant with respect to a change in the codeCD<0:3>. That is to say, in the cases where the code CD<0:3> changesfrom ‘0000’ to ‘0001’, from ‘0001’ to ‘0011’, from ‘0011’ to ‘0111’ andfrom ‘0111’ to ‘1111’, the phase change amounts in the output signals ofthe phase mixer are the same with one another (namely, each time thevalue of the code CD<0:3> is changed by a unit value (for example, 1bit), the phase of the output signal of the phase mixer is changed by aperiod equal to the unit value when the phase difference between thefirst clock FCLK and the second clock SCLK is divided into four equalperiods).

In general, when the phase difference between the first clock FCLK andthe second clock SCLK is small, the phase mixer operates as describedabove. However, as the phase difference between the first clock FCLK andthe second clock SCLK increases, the phase mixer deviates from theabove-described operations.

FIG. 2 is a waveform diagram illustrating a feature in the conventionalphase mixer as the phase difference between the first clock FCLK and asecond clock SCLK increases.

For illustration purposes, the waveforms of the first clock FCLK and thesecond clock SCLK are independently shown in FIG. 2 assuming that thecode CD<0:3> is changed from ‘0000’ sequentially to ‘0001’, ‘0011’ and‘0111’ (the inverted code CDB<0:3> is changed from ‘1111’ sequentiallyto ‘1110’, ‘1100’ and ‘1000’). The waveform of the signal (hereinafter,referred to as a “mixed signal MN”) generated at the mixing node MNcorresponds to a waveform in which the waveform of the first clock FCLKand the waveform of the second clock SCLK are summed with each other (ateach time, the sum of the value of the first clock FCLK and the value ofthe second clock SCLK becomes the value of the mixed signal MN).

Depending upon whether the level of the mixed signal MN is higher orlower than a reference level 201 (the mixed signal MN has a high levelor a low level), a high level or a low level is outputted to the outputnode OUT. Therefore, times A1 to A4 at which the reference level 201 andthe mixed signal MN cross each other correspond to times at which thelogic value of the output signal OUT is changed. Thus, by observing howthe times A1 to A4 at which the reference level 201 and the mixed signalMN cross with each other are moved as the value of the code CD<0:3> ischanged, a change in the phase of the output signal OUT is changed asthe value of the code CD<0:3> is determined.

Referring to FIG. 2, it can be seen that, when the phase differencebetween the first clock FCLK and the second clock SCLK is large, thephase change amounts 202, 203 and 204 of the output signal OUT are notconstant as the code CD<0:3> is changed from ‘0000’ sequentially to‘0001’, ‘0011’ and ‘0111’ (the phase change amounts 202, 203 and 204gradually increase). In other words, when the phase difference betweenthe first clock FCLK and the second clock SCLK is large, the phasechange amounts of the output signal OUT are not constant even though thecode CD<0:3> is sequentially changed by the unit value (for example, 1bit). Due to such features, a jitter is likely to increase in the delaylocked loop.

SUMMARY

An embodiment of the present invention is directed to a phase mixerwhich can mix phases at a precise ratio according to the value of a codefor controlling a mixing ratio even when two signals with a large phasedifference are mixed.

In accordance with an embodiment of the present invention, a phase mixerincludes: a first driver configured to drive a first input signal to amixing node with a driving force determined by a first setting value; asecond driver configured to drive a second input signal to the mixingnode with a driving force determined by a second setting value; and aslew rate control unit configured to control a slew rate at the mixingnode.

In accordance with another embodiment of the present invention, a delaylocked loop includes: a first delay unit configured to delay an inputclock and generate a first clock; a second delay unit configured todelay the input clock and generate a second clock; a first driverconfigured to drive the first clock to a mixing node with a drivingforce determined by a first setting value; a second driver configured todrive the second clock to the mixing node with a driving forcedetermined by a second setting value; a slew rate control unitconfigured to control a slew rate at the mixing node; an bufferconfigured to buffer a signal of the mixing node and output the bufferedsignal to an output node; a replica delay unit configured to delay aclock outputted to the output node and generate a feedback clock; aphase comparison unit configured to compare phases of the input clockand the feedback clock; and a control unit configured to control delayvalues of the first delay unit and the second delay unit in response toa comparison result of the phase comparison unit and generate the firstsetting value and the second setting value.

In accordance with yet another embodiment of the present invention, aphase mixer includes: a phase mixing unit configured to mix a firstinput signal and a second input signal at a ratio determined by settingvalues and output a signal obtained from the mixing to a mixing node;and a slew rate control unit configured to control a slew rate at themixing node.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram of a conventional phase mixer.

FIG. 2 is a waveform diagram illustrating a feature in the conventionalphase mixer as a phase difference between a first clock and a secondclock increases.

FIG. 3 is a configuration diagram of a phase mixer in accordance with anembodiment of the present invention.

FIG. 4 is a waveform diagram illustrating the operations of the phasemixer in accordance with the embodiment of the present invention when aphase difference between a first input signal and a second input signalis larger than a reference value.

FIG. 5 is a configuration diagram of a delay locked loop in accordancewith another embodiment of the present invention.

FIG. 6 is a configuration diagram of a phase mixer in accordance withanother embodiment of the present invention.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

In the following descriptions, a ‘high’ level, a logic ‘high’ value,‘high’, a logic value ‘1’, and ‘1’ each represent a logic high value,and a ‘low’ level, a logic ‘low’ value, ‘low’, a logic value ‘0’, and‘0’ each represent a logic low value. The level of each signal whenactivated may be a ‘high’ level or a ‘low’ level (the level of thesignal when deactivated is opposite to the level of the signal whenactivated) and may be changed for different signals and different designneeds.

FIG. 3 is a configuration diagram of a phase mixer in accordance with anembodiment of the present invention.

Referring to FIG. 3, a phase mixer may include a first driver 310configured to drive a first input signal FCLK to a mixing node MN with adriving force that is determined by a first setting value SET1<0:3>, asecond driver 320 configured to drive a second input signal SCLK to themixing node MN with a driving force that is determined by a secondsetting value SET2<0:3>, a slew rate control unit 330 configured tocontrol a slew rate at the mixing node MN, and an buffer 340 configuredto buffer the signal of the mixing node MN and output the bufferedsignal to an output node OUT.

The first input signal FCLK, the second input signal SCLK and the signal(hereinafter, referred to as an “output signal OUT”) outputted to theoutput node OUT may be clock signals. The slew rate means a maximumvariation rate of an output voltage per unit time and is expressed byV/μs (voltage per microsecond). If the slew rate is large, a speed atwhich the output voltage varies becomes fast, and if the slew rate issmall, the speed at which the output voltage varies becomes slow. Thefirst setting value SET1<0:3> and the second setting value SET2<0:3> maybe binary codes of a single bit or multiple bits. Hereinbelow, binarysignals of 4 bits will be used for illustration purposes.

Hereinafter, operations of the phase mixer will be described withreference to FIG. 3.

The first driver 310 drives the first input signal FCLK to the mixingnode MN with the driving force that is determined in response to thefirst setting value SET1<0:3>. According to an example, the first driver310 may include a plurality of first unit drivers 311 to 314 which areactivated or deactivated in response to the respective bits SET1<0> toSET1<3> of the first setting value SET1<0:3>. Among the plurality offirst unit drivers 311 to 314, one or more first unit driver may beactivated and drive the first input signal FCLK to the mixing node MN,and one or more first unit driver may be deactivated from driving thefirst input signal FCLK to the mixing node MN. Accordingly, dependingupon the number of first unit drivers which are activated among theplurality of first unit drivers 311 to 314, a driving force by which thefirst input signal FCLK is driven to the mixing node MN is determined.While the first unit drivers may be inverters for inverting inputs anddriving the inverted inputs as outputs as can be seen from FIG. 3, thepresent invention is not limited to such. The first unit drivers may becircuits for buffering inputs and driving the buffered inputs as outputsor circuits for transmitting inputs as outputs. The first driver 310 isnot necessarily limited to the configuration shown in FIG. 3, and anycircuits may be used as the first driver 310 so long as they can performan operation of driving the first input signal FCLK to the mixing nodeMN with the driving force that is determined according to the firstsetting value SET1<0:3>.

The second driver 320 drives the second input signal SCLK to the mixingnode MN with the driving force that is determined in response to thesecond setting value SET2<0:3> (that is, SET2<0:3> and SET2B<0:3>). Forthis operation, the second driver 320 may include a plurality of secondunit drivers 321 to 324 which are activated or deactivated in responseto the respective bits SET2<0> to SET2<3> of the second setting valueSET2<0:3>. Among the plurality of second unit drivers 321 to 324, one ormore second unit drivers may be activated and drive the second inputsignal SCLK to the mixing node MN, and one or more second unit driversmay be deactivated from driving the second input signal SCLK to themixing node MN. Accordingly, depending upon the number of second unitdrivers which are activated among the plurality of second unit drivers321 to 324, a driving force by which the second input signal SCLK isdriven to the mixing node MN is determined. While the second unitdrivers may be inverters for inverting inputs and driving the invertedinputs as outputs as can be seen from FIG. 3, the present invention isnot necessarily limited to such. The second unit drivers may be circuitsfor buffering inputs and driving the buffered inputs as outputs orcircuits for transmitting inputs as outputs. The second driver 320 isnot necessarily limited to the configuration shown in FIG. 3, and anycircuits may be used as the second driver 320 so long as they canperform an operation of driving the second input signal SCLK to themixing node MN with the driving force that is determined according tothe second setting value SET2<0:3>.

Here, the sum of the first setting value SET1<0:3> and the secondsetting value SET2<0:3> may be constantly maintained. In particular, inthe case where the sum of the first setting value SET1<0:3> and thesecond setting value SET2<0:3> is constantly maintained as ‘1111’, thefirst setting value SET1<0:3> and the second setting value SET2<0:3> arein a relationship in which their logic values are inverted with respectto each other. For example, if the first setting value SET1<0:3> is‘0011’, the second setting value SET2<0:3> becomes ‘1100’ which isobtained by inverting ‘0011’, and if the first setting value SET1<0:3>is ‘0111’, the second setting value SET2<0:3> becomes ‘1000’ which isobtained by inverting ‘0111’. For reference, SET1B<0:3> is a signalwhich is obtained by inverting the first setting value SET1<0:3>, andSET2B<0:3> is a signal which is obtained by inverting the second settingvalue SET2<0:3>.

The ratio, at which the first input signal FCLK and the second inputsignal SCLK are driven to the mixing node MN according to the firstsetting value SET1<0:3> and the second setting value SET2<0:3>, isdetermined in response to the value of the code CD<0:3> and the value ofthe inverted code CDB<0:3> as described above with reference to FIG. 1.The first setting value SET1<0:3> corresponds to the code CD<0:3>, andthe second setting value SET2<0:3> corresponds to the inverted codeCDB<0:3>.

The slew rate control unit 330 controls a slew rate at the mixing nodeMN. The slew rate control unit 330 decreases the slew rate at the mixingnode MN if a phase difference between the first input signal FCLK andthe second input signal SCLK is larger than a reference value. That isto say, if a phase difference between the first input signal FCLK andthe second input signal SCLK is larger than the reference value, theslew rate control unit 330 causes the voltage of the mixing node MN tovary slow (the slope of a waveform decreases in the graph showing achange in the voltage of the mixing node MN with respect to a time).Hereinafter, the reference numeral 330A represents a first example ofthe slew rate control unit 330, and the reference numeral 3308represents a second example of the slew rate control unit 330.

For the above-described operation, in the first exemplary embodiment330A, the slew rate control unit 330 may include a transistor 331Ahaving one end connected to the mixing node MN and the other endconnected to an internal node NO and turned on or off in response to acontrol signal SL which is activated when the phase difference betweenthe first input signal FCLK and the second input signal SCLK is largerthan the reference value, and a capacitor 332A having one end which isconnected to the internal node NO and the other end to which a groundvoltage VSS is applied. The positions of the transistor 331A and thecapacitor 332A may be changed with each other. Namely, the capacitor332A may be connected between the mixing node MN and the internal nodeNO, and the transistor 331A may have one end connected to the internalnode NO and the other end to which the ground voltage VSS is applied.

The capacitor 332A performs a function of stabilizing the voltage of thenode connected thereto from fluctuating. Therefore, if the controlsignal SL is activated (has a high level), the transistor 331A is turnedon, and the one end of the capacitor 332A is electrically connected tothe mixing node MN. Due to this fact, a speed at which the voltage ofthe mixing node MN is changed becomes slow (a slew rate decreases).Conversely, if the control signal SL is deactivated (has a low level),the transistor 332A is turned off, and the mixing node MN and the oneend of the capacitor 332A are electrically disconnected from each other.Due to this fact, a speed at which the voltage of the mixing node MN ischanged becomes fast (a slew rate increases).

Otherwise, in the second exemplary embodiment 330B, the slew ratecontrol unit 330 may include a transistor 331B having one end which isconnected to the mixing node MN and turned on or off in response to thecontrol signal SL which is activated when the phase difference betweenthe first input signal FCLK and the second input signal SCLK is largerthan the reference value, and a resistive element 332B having one endconnected to the mixing node MN and the other end connected to the otherend of the transistor 3318.

Since the resistive element 332B limits current flow, it performs afunction of preventing the voltage of the node connected thereto frombeing changed. Therefore, if the control signal SL is activated (has ahigh level), the transistor 331B is turned off, and current flowsthrough the resistive element 332B between the mixing node MN and theinput end of the buffer 340. Due to this fact, a speed at which thevoltage of the mixing node MN is changed becomes slow (a slew ratedecreases). Conversely, if the control signal SL is deactivated (has alow level), the transistor 331B is turned on, and the mixing node MN andthe input end of the buffer 340 are electrically connected with eachother via the transistor 331B. Accordingly, current does not flowthrough the resistive element 332B but through the transistor 331Bbetween the mixing node MN and the input end of the buffer 340.Therefore, since current flow is not limited by the resistive element332B, a speed at which the voltage of the mixing node MN is changedbecomes fast (a slew rate increases).

While it is illustrated in FIG. 3 that the slew rate control unit 330includes any one of the capacitor 332A and the resistive element 332B,the slew rate control unit 330 may include both the capacitor 332A andthe resistive element 332B. A degree at which a slew rate is changed atthe mixing node MN may be controlled by controlling the capacitancevalue of the capacitor 332A and the resistance value of the resistiveelement 332B.

The reason why the slew rate control unit 330 is activated when thephase difference between the first input signal FCLK and the secondinput signal SCLK is larger than the reference value and is deactivatedwhen the phase difference is smaller than the reference value is asfollows. As aforementioned with reference to FIG. 2, the feature where aphase change amount of the output signal OUT according to a change inthe code CD<0:3> is not constant is likely to occur as the phasedifference between the first input signal FCLK and the second inputsignal SCLK becomes large. In this regard, if the slew rate at themixing node MN is decreased so as to address such a feature, sincesignal transmission is correspondingly delayed, the high speed operationof the phase mixer is limited (that is, if the slew rate is low, thephase mixer does not appropriately operate when a high frequency signalis inputted). Therefore, since reducing a jitter and improvingperformance at a high frequency are at an inverse proportionalrelationship to one another, the reference value is preset such that theslew rate can be decreased by activating the slew rate control unit 330when the phase difference between the first input signal FCLK and thesecond input signal SCLK is larger than the reference value and can beincreased by deactivating the slew rate control unit 330 when the phasedifference between the first input signal FCLK and the second inputsignal SCLK is smaller than the reference value. More specifically,according an example, only when the phase difference between the inputsignals is large, the slew rate is decreased at the mixing node MN toreduce a jitter, and when the phase difference between the input signalsis small, the slew rate is increased at the mixing node MN to ensure thehigh speed operation of the phase mixer.

The buffer 340 buffers the signal of the mixing node MN and outputs thebuffered signal to the output node OUT. According to an example, thebuffer 340 may include an inverter which outputs a high level to theoutput node OUT when the voltage level of the mixing node MN is smallerthan a reference level (a logic threshold) (when the mixing node MN hasa low level) and outputs a low level to the output node OUT when thevoltage level of the mixing node MN is larger than the reference level(when the mixing node MN has a high level). However, exemplaryembodiments of the present invention are not limited to such an example.It is sufficient that the buffer 340 includes a circuit which outputs anoutput signal with a high level or a low level depending upon whether aninput signal is lower or higher than a reference level (as in aninverter, the circuit may output the output signal with a logic valueopposite to the logic value of the input signal or may output the outputsignal with the same logic value as the logic value of the inputsignal). The slew rate control unit 330 is directly linked to the buffer340 through the mixing node MN.

Describing the entire operations of the phase mixer, the first driver310 drives the first input signal FCLK to the mixing node MN with thedriving force that is determined by the first setting value SET1<0:3>.The second driver 320 drives the second input signal SCLK to the mixingnode MN with the driving force that is determined by the second settingvalue SET2<0:3>. At this time, according to the driving forces of thefirst driver 310 and the second driver 320, the waveform of the voltageof the mixing node MN is changed, and due to this fact, the phase of theoutput signal OUT is changed. The phase of the output signal OUT has avalue between the phase of the first input signal FCLK and the phase ofthe second input signal SCLK, and the precise value thereof variesdepending upon the first setting value SET1<0:3> and the second settingvalue SET2<0:3>. The slew rate control unit 330 is activated when thephase difference between the first input signal FCLK and the secondinput signal SCLK is larger than the reference value and decreases theslew rate of the voltage of the mixing node MN to ensure that a phasechange amount of the output signal OUT according to changes in the firstsetting value SET1<0:3> and the second setting value SET2<0:3> isconstant.

In the phase mixer in accordance with the embodiment of the presentinvention, when the phase difference between the first input signal FCLKand the second input signal SCLK is larger than the reference value, theslew rate of the voltage of the mixing node MN is decreased to ensurethat a phase change amount of the output signal OUT according to changesin the first setting value SET1<0:3> and the second setting valueSET2<0:3> is constant. Also, when the phase difference between the firstinput signal FCLK and the second input signal SCLK is larger than thereference value, the slew rate of the voltage of the mixing node MN isnot decreased to ensure the high frequency operation of the phase mixer.

FIG. 4 is a waveform diagram illustrating the operations of the phasemixer in accordance with the embodiment of the present invention when aphase difference between the first input signal FCLK and the secondinput signal SCLK is larger than the reference value.

For illustration purposes, the waveforms of the first clock FCLK and thesecond clock SCLK are independently shown in FIG. 4. The waveform of thesignal (hereinafter, referred to as a “mixed signal MN”) generated inthe mixing node MN corresponds to a waveform in which the waveform ofthe first input signal FCLK and the waveform of the second input signalSCLK are summed with each other (at each time, the sum of the value ofthe first input signal FCLK and the value of the second input signalSCLK becomes the value of the mixed signal MN).

Here, waveforms corresponding to the first setting value SET1<0:3> aresequentially shown as the first setting value SET1<0:3> is changed inthe same manner as the code CD<0:3> in FIG. 2 (the second setting valueSET2<0:3> is changed in the same manner as the inverted code CDB<0:3> inFIG. 2). The first setting value SET1<0:3> has the same value as thecode CD<0:3> of FIG. 2, and the second setting value SET2<0:3> has thesame value as the inverted code CDB<0:3>.

Depending upon whether the level of the mixed signal MN is higher orlower than a reference level 401 (the level of the mixed signal MN ishigh or low), a high level or a low level is outputted to the outputnode OUT. Therefore, times A1 to A4 at which the reference level 401 andthe mixed signal MN cross each other correspond to times at which thelogic value of the output signal OUT is changed. Thus, by observing howthe times A1 to A4 at which the reference level 401 and the mixed signalMN cross each other are moved as the value of the first setting valueSET1<0:3> is changed, the phase change amount of the output signal OUTis determined as the value of the first setting value SET1<0:3> ischanged.

As can be seen from FIG. 4, in the phase mixer in accordance with theembodiment of the present invention shown in FIG. 3, unlike theconventional phase mixer, even though the phase difference between thefirst input signal FCLK and the second input signal SCLK is large, phasechange amounts 402, 403 and 404 of the output signal OUT according tochanges in the first setting value SET1<0:3> and the second settingvalue SET2<0:3> are constant.

FIG. 5 is a configuration diagram of a delay locked loop in accordancewith another embodiment of the present invention. The delay locked loopshown in FIG. 5 includes the phase mixer shown in FIG. 3.

Referring to FIG. 5, the delay locked loop includes a first delay unit510 configured to delay an input clock ICLK and generate a first clockFCLK, a second delay unit 520 configured to delay the input clock ICLKand generate a second clock SCLK, a phase mixing unit 530 configured tomix the phases of the first clock FCLK and the second clock SCLK inresponse to a first setting value SET1<0:3> and a second setting valueSET2<0:3> and generate an output clock OCLK, a replica delay unit 540configured to delay the output clock OCLK and generate a feedback clockFBCLK, and a phase comparison unit 550 configured to compare the phasesof the input clock ICLK with the feedback clock FBCLK, and a controlunit 560 configured to control the delay values of the first delay unit510 and the second delay unit 520 in response to a comparison result ofthe phase comparison unit 550 and generate the first setting valueSET1<0:3> and the second setting value SET2<0:3>.

Hereinafter, operations of the delay locked loop will be described withreference to FIG. 5.

The first delay unit 510 and the second delay unit 520 delay the inputclock ICLK and respectively output the first clock FCLK and the secondclock SCLK. The delay values of the first delay unit 510 and the seconddelay unit 520 are changed by a first unit delay value or a second unitdelay value at a time according to a comparison result of the phasecomparison unit 550.

According to an example, the first delay unit 510 includes a pluralityof first unit delay units 511 which have the first unit delay value asthe delay value and are activated or deactivated by the control unit560, and a plurality of second unit delay units 512 which have thesecond unit delay value larger than the first unit delay value as thedelay value and are activated or deactivated by the control unit 560.Also, the second delay unit 520 includes a plurality of third unit delayunits 521 which have the first unit delay value as the delay value andare activated or deactivated by the control unit 560, and a plurality offourth unit delay units 522 which have the second unit delay value asthe delay value and are activated or deactivated by the control unit560. The delay value of the first delay unit 510 and the delay value ofthe second delay unit 520 may have a difference corresponding to thefirst unit delay value or the second unit delay value. According to anexample, the first delay unit 510 and the second delay unit 520correspond to a coarse delay line of a delay locked loop whichrelatively coarsely controls the delay value of the output clock OCLK.

The configuration and operation of the phase mixing unit 530 are thesame as the phase mixer shown in FIG. 3. More specifically, the phasemixing unit 530 includes a first driver 310, a second driver 320, a slewrate control unit 330, and an buffer 340. The first clock FCLKcorresponds to the first input signal FCLK, the second clock SCLKcorresponds to the second input signal SCLK, and the output clock OCLKcorresponds to the output signal OUT (the signal outputted to the outputnode OUT). For illustration purposes, it is assumed that the first unitdelay value is smaller than the reference value described above indetail with reference to FIG. 3 and the second unit delay value islarger than the reference value. Thus, if the difference between thedelay value of the first delay unit 510 and the delay value of thesecond delay unit 520 corresponds to the first unit delay value, theslew rate control unit 330 is deactivated, and if the difference betweenthe delay value of the first delay unit 510 and the delay value of thesecond delay unit 520 corresponds to the second unit delay value, theslew rate control unit 330 is activated. According to an example, thephase mixing unit 530 corresponds to a fine delay line of a delay lockedloop which finely controls the phase of the output clock OCLK.

The replica delay unit 540 outputs the feedback clock FBCLK by delayingthe output clock OCLK by a delay value acquired through modeling a clockdelay component inside a semiconductor device (for example, asemiconductor memory device) in which a delay locked loop is included,and the phase comparison unit 550 outputs a result of comparing theinput clock ICLK and the feedback clock FBCLK.

The control unit 560 controls the delay values of the first delay unit510 and the second delay unit 520 according to the comparison result ofthe phase comparison unit 550, and generates the first setting valueSET1<0:3> and the second setting value SET2<0:3>. Namely, the controlunit 560 controls the delay value of the output clock OCLK according tothe comparison result of the phase comparison unit 550. In the casewhere the phase of the input clock ICLK is earlier than the phase of thefeedback clock FBCLK, the control unit 560 decreases the delay value ofthe output clock OCLK, and in an opposite case, the control unit 560increases the delay value of the output clock OCLK. Moreover, in orderto control the slew rate control unit 330, when the difference betweenthe delay value of the first delay unit 510 and the delay value of thesecond delay unit 520 corresponds to the first unit delay value, thecontrol unit 560 deactivates the control signal SL (deactivates the slewrate control unit 330), and when the difference between the delay valueof the first delay unit 510 and the delay value of the second delay unit520 corresponds to the second unit delay value, the control unit 560activates the control signal SL (activates the slew rate control unit330).

According to an example, if the delay value of the first delay unit 510and the delay value of the second delay unit 520 are changed by thefirst unit delay value at a time, the difference between the delay valueof the first delay unit 510 and the delay value of the second delay unit520 corresponds to the first unit delay value, and if the delay value ofthe first delay unit 510 and the delay value of the second delay unit520 are changed by the second unit delay value at a time, the differencebetween the delay value of the first delay unit 510 and the delay valueof the second delay unit 520 corresponds to the second unit delay value.Accordingly, the control unit 560 may deactivate the control signal SLwhen the delay value of the first delay unit 510 and the delay value ofthe second delay unit 520 are changed by the first unit delay value at atime and may activate the control signal SL when the delay value of thefirst delay unit 510 and the delay value of the second delay unit 520are changed by the second unit delay value at a time.

Hereinbelow, operations of the delay locked loop will be describedmainly with respect to the operation of the phase mixing unit 530.

First, if a delay locking operation is started, the first delay unit 510and the second delay unit 520 delay the input clock ICLK by a minimumdelay value and generate the first clock FCLK and the second clock SCLK.The phase mixing unit 530 mixes the phases of the first clock FCLK andthe second clock SCLK according to the initial setting values (theinitial values of SET1<0:3> and SET2<0:3>) and generates the outputclock OCLK. The replica delay unit 540 delays the output clock OCLK andgenerates the feedback clock FBCLK, and the phase comparison unit 550compares the phases of the input clock ICLK and the feedback clockFBCLK. According to a phase comparison result of the phase comparisonunit 550, the phase of the output clock OCLK is changed by the firstunit delay value or the second unit delay value (the phase of the outputclock OCLK is controlled by the first delay unit 510 and the seconddelay unit 520: hereinafter, referred to as a ‘coarse control step’).Subsequently, according to a phase comparison result of the phasecomparison unit 550, if the phase difference between the input clockICLK and the feedback clock FBCLK becomes smaller than the first unitdelay value or the second unit delay value, the phase of the outputclock OCLK is finely controlled by the phase mixing unit 530(hereinafter, referred to as a ‘fine control step’).

In the case where the phase difference between the first clock FCLK andthe second clock SCLK corresponds to the first unit delay value, sincethe first unit delay value is smaller than the reference value, the slewrate control unit 330 of the phase mixing unit 530 is in the deactivatedstate (the control signal SL is deactivated). In the case where thephase difference between the first clock FCLK and the second clock SCLKcorresponds to the second unit delay value, since the second unit delayvalue is larger than the reference value, the slew rate control unit 330of the phase mixing unit 530 is in the activated state (the controlsignal SL is activated). Accordingly, in the delay locked loop accordingto the exemplary embodiment of the present invention, even when thephase difference between the first clock FCLK and the second clock SCLKbecomes the second unit delay value (that is, becomes larger than thereference value), the phase change amount of the output clock OCLKaccording to a change in the setting values SET1<0:3> and SET2<0:3> isconstantly maintained (the phase is changed by ¼ times the second unitdelay value each time the setting values SET1<0:3> and SET2<0:3> arechanged by one bit).

Even in the case of a delay locked loop which uses the conventionalphase mixer, if the phase difference between the first clock FCLK andthe second clock SCLK corresponds to the first unit delay value (thatis, is smaller than the reference value), the phase change amount of theoutput clock OCLK according to a change in the setting values SET1<0:3>and SET2<0:3> is constant to ¼ times the first delay value. However, asaforementioned in detail with reference to FIGS. 1 and 2, if the phasedifference between the first clock FCLK and the second clock SCLKcorresponds to the second unit delay value (larger than the referencevalue), the phase change amount of the output clock OCLK according to achange in the setting values SET1<0:3> and SET2<0:3> is not constant at¼ times the second delay value.

In the delay locked loop using the phase mixer in accordance with theembodiment of the present invention, even when the phase differencebetween the first clock FCLK and the second clock SCLK is larger thanthe second unit delay value (larger than the reference value), the phasechange amount of the output clock OCLK according to a change in thesetting values SET1<0:3> and SET2<0:3> is constantly maintained at ¼times the second unit delay value by controlling the slew rate of themixing node MN using the slew rate control unit 330 included in thephase mixing unit 530, whereby a jitter is reduced.

Here, the reason why the first delay unit 510 and the second delay unit520 include the second and fourth unit delay units 512 and 522 with thesecond unit delay value as the delay value is that, if unit delay unitswith a large delay value are used, the number of unit delay unitsnecessary for obtaining the same delay value is decreased compared towhen unit delay units with a small delay value are used, and thus, thenumber of registers for controlling unit delay units is decreased tothus reduce the area of a delay locked loop.

FIG. 6 is a configuration diagram of a phase mixer in accordance withanother embodiment of the present invention.

Referring to FIG. 6, the phase mixer includes a phase mixing unit 610configured to mix the phases of a first input signal FCLK and a secondinput signal SCLK at a ratio determined by setting values SET1<0:3> andSET2<0:3> and outputting a resultant signal to a mixing node MN, a slewrate control unit 620 configured to control a slew rate at the mixingnode MN, and an buffer 630 configured to buffer the signal of the mixingnode MN and output the buffered signal to the an output node OUT. Thephase mixing unit 610 mixes the phases of the first input signal FCLKand the second input signal SCLK at the ratio determined in response tothe setting values SET1<0:3> and SET2<0:3> and outputs the resultantsignal to the mixing node MN. According to an example, the phase mixingunit 610 may include the first driver 310 and the second driver 320shown in FIG. 3. In other words, the phase mixing unit 610 may drive thefirst input signal FCLK and the second input signal SCLK to the mixingnode MN at the ratio determined in response to the setting valuesSET1<0:3> and SET2<0:3> and thereby may output the signal obtained bymixing the phases of the first input signal FCLK and the second inputsignal SCLK at the ratio determined according to the setting valuesSET1<0:3> and SET2<0:3> at the mixing node MN. Detailed operations ofthe phase mixing unit 610 are the same as described with reference toFIG. 3. However, the configuration of the phase mixing unit 610 is notnecessarily limited to the configuration including the first driver 310and the second driver 320 shown in FIG. 3, and all circuits may be usedas the phase mixing unit 610 so long as they can perform an operation ofmixing the phases of the first input signal FCLK and the second inputsignal SCLK at the ratio determined according to the setting valuesSET1<0:3> and SET2<0:3>.

The configuration and operations of the slew rate control unit 620 arethe same as those of the slew rate control unit 330 shown in FIG. 3.According to an example, the slew rate control unit 620 includes atransistor 621 to be turned on or off by receiving a control signal SLand a capacitor 622. Here, the slew rate control unit 620 may include atransistor or a resistive element or both of a transistor and aresistive element as described above in detail with reference to FIG. 3.Furthermore, the first exemplary embodiment 330A of the slew ratecontrol unit 330 shown in FIG. 3 and the slew rate control unit 620shown in FIG. 6 are circuits for performing substantially the samefunction while a sequence in which the transistor and the capacitor areconnected is different.

The configuration and operations of the buffer 630 are the same as thoseof the buffer 340 shown in FIG. 3.

The phase mixer shown in FIG. 6 operates in the same manner and has thesame effects as the phase mixer shown in FIG. 3.

As is apparent from the above descriptions, in the phase mixer inaccordance with the embodiments of the present invention, a signal isobtained by mixing two signals at a precise ratio according to the valueof a code for controlling a mixing ratio (for example, by decreasing aslew rate at a node to which the two signals are driven when a phasedifference between the two signals to be mixed is large).

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

What is claimed is:
 1. A phase mixer comprising: a first driverconfigured to drive a first input signal to a mixing node with a drivingforce determined by a first setting value; a second driver configured todrive a second input signal to the mixing node with a driving forcedetermined by a second setting value; and a slew rate control unitconfigured to control a slew rate at the mixing node.
 2. The phase mixerof claim 1, wherein the slew rate control unit is configured to beactivated when a phase difference between the first input signal and thesecond input signal is larger than a reference value.
 3. The phase mixerof claim 2, wherein the slew rate control unit comprises: a transistorhaving one end connected to the mixing node and the other end connectedto an internal node and turned on/off in response to a control signal,wherein the control signal is activated when the phase differencebetween the first input signal and the second input signal is largerthan the reference value; and a capacitor having one end connected tothe internal node and the other end connected to receive a groundvoltage.
 4. The phase mixer of claim 2, wherein the slew rate controlunit comprises: a transistor having one end connected to the mixing nodeand turned on/off in response to a control signal, wherein the controlsignal is activated when the phase difference between the first inputsignal and the second input signal is larger than the reference value;and a resistive element having one end connected to the mixing node andthe other end connected to the other end of the transistor.
 5. The phasemixer of claim 1, wherein a sum of the first setting value and thesecond setting value is maintained at a constant value.
 6. The phasemixer of claim 1, further comprising: an buffer configured to buffer asignal of the mixing node and output the buffered signal to an outputnode.
 7. The phase mixer of claim 1, wherein the first driver comprisesa plurality of first unit drivers configured to be activated ordeactivated in response to respective bits of the first setting value,and wherein the second driver comprises a plurality of second unitdrivers configured to be activated or deactivated in response torespective bits of the second setting value.
 8. The phase mixer of claim6, wherein the first input signal, the second input signal and thesignal outputted to the output node comprise clock signals.
 9. A delaylocked loop comprising: a first delay unit configured to delay an inputclock and generate a first clock; a second delay unit configured todelay the input clock and generate a second clock; a first driverconfigured to drive the first clock to a mixing node with a drivingforce determined by a first setting value; a second driver configured todrive the second clock to the mixing node with a driving forcedetermined by a second setting value; a slew rate control unitconfigured to control a slew rate at the mixing node; an bufferconfigured to buffer a signal of the mixing node and output the bufferedsignal to an output node; a replica delay unit configured to delay aclock outputted to the output node and generate a feedback clock; aphase comparison unit configured to compare phases of the input clockand the feedback clock; and a control unit configured to control delayvalues of the first delay unit and the second delay unit in response toa comparison result of the phase comparison unit and generate the firstsetting value and the second setting value.
 10. The delay locked loop ofclaim 9, wherein the control unit is configured to activate the slewrate control unit when a phase difference between the first clock andthe second clock is larger than a reference value.
 11. The delay lockedloop of claim 10, wherein the slew rate control unit comprises: atransistor having one end connected to the mixing node and the other endconnected to an internal node and turned on/off in response to a controlsignal, wherein the control signal is activated when the phasedifference between the first clock and the second clock is larger thanthe reference value; and a capacitor having one end connected to theinternal node and the other end connected to receive a ground voltage.12. The delay locked loop of claim 10, wherein the slew rate controlunit comprises: a transistor having one end connected to the mixing nodeand the other end connected to an input of the buffer and turned on/offin response to a control signal, wherein the control signal is activatedwhen the phase difference between the first clock and the second clockis larger than the reference value; and a resistive element having oneend connected to the mixing node and the other end connected to theother end of the transistor.
 13. The delay locked loop of claim 9,wherein a sum of the first setting value and the second setting value ismaintained at a constant value.
 14. The delay locked loop of claim 10,wherein the first delay unit comprises: a plurality of first unit delayunits each having a delay of a first unit delay value; and a pluralityof second unit delay units having a delay of a second unit delay valuelarger than the first unit delay value, and wherein the second unitdelay unit comprises: a plurality of third unit delay units having adelay of the first unit delay value; and a plurality of fourth unitdelay units having a delay of the second unit delay value.
 15. The delaylocked loop of claim 14, wherein the phase difference between the firstclock and the second clock corresponds to the first unit delay value orthe second unit delay value and the first unit delay value is smallerthan the reference value and the second unit delay value is larger thanthe reference value.
 16. The delay locked loop of claim 9, wherein thefirst driver comprises a plurality of first unit drivers configured tobe activated or deactivated in response to respective bits of the firstsetting value, and wherein the second driver comprises a plurality ofsecond unit drivers configured to be activated or deactivated inresponse to respective bits of the second setting value.
 17. A phasemixer comprising: a phase mixing unit configured to mix a first inputsignal and a second input signal at a ratio determined by setting valuesand output a signal obtained from the mixing to a mixing node; and aslew rate control unit configured to control a slew rate at the mixingnode.
 18. The phase mixer of claim 17, wherein the slew rate controlunit is configured to be activated when a phase difference between thefirst input signal and the second input signal is larger than areference value.
 19. The phase mixer of claim 18, wherein the slew ratecontrol unit comprises: a transistor having one end connected to themixing node and the other end connected to an internal node and turnedon/off in response to a control signal, wherein the control signal isactivated when the phase difference between the first input signal andthe second input signal is larger than the reference value; and acapacitor having one end connected to the internal node and the otherend connected to receive a ground voltage.
 20. The phase mixer of claim18, wherein the slew rate control unit comprises: a transistor havingone end connected to the mixing node and turned on/off in response to acontrol signal, wherein the control signal is activated when the phasedifference between the first input signal and the second input signal islarger than the reference value; and a resistive element having one endconnected to the mixing node and the other end connected to the otherend of the transistor.